ICs use various sorts of devices to create logic circuits. Many types of ICs use complementary metal-oxide-semiconductor (“CMOS”) logic circuits. CMOS logic circuits use CMOS cells that have a first-conductivity-type metal-oxide-semiconductor (“MOS”) transistor (e.g. a p-type MOS (“PMOS”) transistor) paired with a second-conductivity-type MOS transistor (e.g. an n-type MOS (“NMOS”) transistor). CMOS cells can hold a logic state while drawing only very small amounts of current.
It is generally desirable that MOS transistors provide good conductivity between the source and the drain of the MOS transistor when operating voltage is applied to the gate of the MOS transistor. In other words, it is desirable that current flows through the channel between the source and the drain when the MOS transistor is turned on.
The amount of current flowing through the channel of an MOS transistor is proportional to the mobility of charge carriers in the channel. Increasing the mobility of the charge carriers increases the amount of current that flows at a given gate voltage. Higher current flow through the channel allows the MOS transistor to operate faster. One of the ways to increase carrier mobility in the channel of a MOS transistor is to produce strain in the channel.
There are several ways to create strain in the channel region. One approach is to form stressed materials, such as epitaxially grown SiGe, in the source and drain regions of a PMOS transistor. Unfortunately, many conventional processes form embedded SiGe that abuts oxide used for isolation (e.g., shallow-trench isolation (“STI”)) between MOS devices. However, epitaxial SiGe does not grow on the oxide, so the SiGe inserts grow from the bottom of the insert pockets (recesses) formed in the semiconductor wafer (e.g., crystalline silicon) and form facets that grow into the oxide. The oxide is relatively soft, which results in less SiGe-induced stress in the channel of the PMOS device at the opposite end of the SiGe insert.
Techniques have been developed to form SiGe inserts so that they are within recesses in the semiconductor wafer, without the SiGe adjoining the isolation oxide. Disposable gate structures are formed on the isolation oxide when the active (MOS FET) gates are formed. Sidewall (offset) spacers formed on the active gate to self-align drain/source areas of the FET to the active gate are also formed on the disposable gate structures. When the recesses (pockets) for the growing the epitaxial SiGe are formed, the edge of the recess is offset from the isolation oxide by the thickness of the sidewall spacers on the disposable gate structure.
Unfortunately, the optimum offset from the isolation oxide may not be equal to the optimum gate electrode-drain/source offset, particularly at fine device geometries. Similarly, the disposable gate structures extend across the isolation oxide for the offset spacers to provide the desired semiconductor for the SiGe pockets. The active gate structures are frequently a different width than the isolation oxide. In very geometry FETs, the active gate may be much narrower (as measured along the channel length of the FET) than the isolation oxide. Disposable gate structures provide beneficial mechanical support when performing chemical-mechanical polishing or other wafer processing; however, such benefits are degraded when the disposable gate structures are much wider than the active gate structures.
Techniques for enhancing carrier mobility in PMOS FETs using SiGe inserts that avoid the disadvantages of the prior art are desirable.